Stacken/c64-livecoding
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Switched CLC ROR to LSR. 2% performance improvment

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hugova 2025-03-24 17:45:22 +01:00
parent ed0966c736
commit f583423bb6
2 changed files with 20 additions and 6 deletions
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5
wip-hugo/routines/line/line_down.s
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@ -10,7 +10,6 @@
.proc line_down .proc line_down
.include "line.inc"; Defines memory positions, ex X_pos .include "line.inc"; Defines memory positions, ex X_pos
;;We need to clear this memory ;;We need to clear this memory
LDA #$00 LDA #$00
STA <V STA <V
@ -60,8 +59,8 @@ for_x:
ORA (>btp_mem_pos), Y ORA (>btp_mem_pos), Y
STA (>btp_mem_pos), Y STA (>btp_mem_pos), Y
increment_pixel_x: increment_pixel_x:
CLC ;CLC
ROR byte_to_paint LSR byte_to_paint
BCS move_8px_left BCS move_8px_left
JMP increment_pixel_x_end JMP increment_pixel_x_end
move_8px_left: move_8px_left:

21
wip-hugo/routines/line/line_test_time.s
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@ -1,6 +1,9 @@
;;; -*- Mode: asm; indent-tabs-mode: t; tab-width: 8 -*- ;;; -*- Mode: asm; indent-tabs-mode: t; tab-width: 8 -*-
.include "line.inc" .include "line.inc"
;;START TIME HERE
;;for testing stuff ;;for testing stuff
Y_pos_ = $0D Y_pos_ = $0D
X_pos_ = $0E X_pos_ = $0E
@ -15,8 +18,7 @@
LDA #$30 LDA #$30
STA Y_end STA Y_end
;; Short test for timing
time_start
@loop:;; mem f1 @loop:;; mem f1
LDA Y_pos_ LDA Y_pos_
STA Y_pos STA Y_pos
@ -30,7 +32,20 @@
BEQ end__ BEQ end__
jmp @loop jmp @loop
end__: end__:
time_stop ;;Lets cleer bitmap
LDA #>VIC_bank
STA $FC
LDA #<VIC_bank
STA $FB
LDA #>$5f3f
STA $FE
LDA #<$5f3f
STA $FD
LDA #$0
jsr memory_rec
jmp exit jmp exit
.include "line_down.s" .include "line_down.s"