79 lines
3.8 KiB
ArmAsm
79 lines
3.8 KiB
ArmAsm
.scope raster_irq
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;;https://codebase64.org/doku.php?id=base:introduction_to_raster_irqs
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sei ;disable maskable IRQs
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lda #$7f
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sta $dc0d ;disable timer interrupts which can be generated by the two CIA chips
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sta $dd0d ;the kernal uses such an interrupt to flash the cursor and scan the keyboard, so we better
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;stop it.
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lda $dc0d ;by reading this two registers we negate any pending CIA irqs.
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lda $dd0d ;if we don't do this, a pending CIA irq might occur after we finish setting up our irq.
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;we don't want that to happen.
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lda #$01 ;this is how to tell the VICII to generate a raster interrupt
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sta $d01a
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lda #$0FF ;this is how to tell at which rasterline we want the irq to be triggered
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sta $d012
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lda #$1b ;as there are more than 256 rasterlines, the topmost bit of $d011 serves as
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sta $d011 ;the 9th bit for the rasterline we want our irq to be triggered.
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;here we simply set up a character screen, leaving the topmost bit 0.
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lda #$35 ;we turn off the BASIC and KERNAL rom here
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sta $01 ;the cpu now sees RAM everywhere except at $d000-$e000, where still the registers of
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;SID/VICII/etc are visible
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lda #<irq ;this is how we set up
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sta $fffe ;the address of our interrupt code
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lda #>irq
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sta $ffff
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cli ;enable maskable interrupts again
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jmp irq_end
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irq:
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;Being all kernal irq handlers switched off we have to do more work by ourselves.
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;When an interrupt happens the CPU will stop what its doing, store the status and return address
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;into the stack, and then jump to the interrupt routine. It will not store other registers, and if
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;we destroy the value of A/X/Y in the interrupt routine, then when returning from the interrupt to
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;what the CPU was doing will lead to unpredictable results (most probably a crash). So we better
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;store those registers, and restore their original value before reentering the code the CPU was
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;interrupted running.
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;If you won't change the value of a register you are safe to not to store / restore its value.
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;However, it's easy to screw up code like that with later modifying it to use another register too
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;and forgetting about storing its state.
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;The method shown here to store the registers is the most orthodox and most failsafe.
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sei
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pha ;store register A in stack
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txa
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pha ;store register X in stack
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tya
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pha ;store register Y in stack
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lda #$ff ;this is the orthodox and safe way of clearing the interrupt condition of the VICII.
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sta $d019 ;if you don't do this the interrupt condition will be present all the time and you end
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;up having the CPU running the interrupt code all the time, as when it exists the
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;interrupt, the interrupt request from the VICII will be there again regardless of the
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;rasterline counter.
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;it's pretty safe to use inc $d019 (or any other rmw instruction) for brevity, they
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;will only fail on hardware like c65 or supercpu. c64dtv is ok with this though.
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pla
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tay ;restore register Y from stack (remember stack is FIFO: First In First Out)
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pla
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tax ;restore register X from stack
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pla ;restore register A from stack
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clc
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rti ;Return From Interrupt, this will load into the Program Counter register the address
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;where the CPU was when the interrupt condition arised which will make the CPU continue
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;the code it was interrupted at also restores the status register of the CPU
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irq_end:
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.endscope
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