hugova f583423bb6 Switched CLC ROR to LSR. 2% performance improvment		2025-03-24 17:45:22 +01:00
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line	Switched CLC ROR to LSR. 2% performance improvment	2025-03-24 17:45:22 +01:00
memory	Change of starting condition for potential testing purposes of another person	2025-03-09 23:53:33 +01:00